Complex integrated circuit (IC) designs are typically composed of a multitude of standard cells (referred to herein simply as “cells”) that are copied from a standard cell library and placed at selected locations within the IC design. Each standard cell represents a pre-designed circuit portion that performs a designated function and is described using several levels of abstraction typically including a logical view, a netlist view and a layout view. The logic view of a given cell describes, for example, the Boolean logic functions performed by the cell's pre-designed circuit portion. The netlist (or schematic) view of each cell typically includes a SPICE-based netlist file that provides a nodal description of the cell's circuit portion, including active elements (e.g., transistors), passive elements (e.g., resistors and capacitors), parasitic elements (e.g., capacitances or inductances generated by adjacent element structures), and all interconnect structures (e.g., metal lines and inter-metal via structures, referred to herein as “signal paths”) that collectively form the pre-designed circuit portion, and provides an accurate prediction of output signal responses to different patterns of input signals applied to input pins of the pre-designed circuit portion. The layout view of each cell provides an effective fabrication blueprint (i.e., a series of photolithographic mask/reticle patterns) that is utilized during fabrication to produce a physical instantiation of the pre-designed circuit portion in one or more designated regions of a physical IC device. For brevity, unless otherwise specified, references to “cell” or “standard cell” herein refer to a cell's netlist view, even if a corresponding figure appears to depict another view.
Modern IC designs greatly benefit from the use of standard cells. Such IC devices are the product of a design and fabrication process that typically involves the use of one or more electronic design automation (EDA) software tools. These EDA software tools significantly reduce the design process by way of allowing IC designers to select cells from the available cell library that perform needed circuit functions, and to place the cells in designated locations of a software-based IC design such that the cells' netlists are automatically operably connected to the netlists of adjacent cells or custom circuitry, which facilitates software-based verification that the assembled IC design will perform a desired circuit function. In addition, because standard cells are provided with layout views, the use of standard cells greatly simplifies the fabrication process by avoiding the need for circuit designers to generate layout details for the corresponding circuit portions.
Although the use of standard cells greatly simplifies the design and fabrication process, the number of manufacturing defects associated with the fabrication of standard cells has increased as the minimum features sizes of state-of-the-art fabrication processes nodes continues to decrease. A problem with technology scaling is that it can produce unexpected manufacturing (physical) defects (e.g., shorts, opens, and transistor defects) within physical implementations of the associated standard cells, thereby affecting manufacturing yields by causing a significant number of the host IC devices to fail. Recently, manufacturing (fabrication) defects within standard cells has been recognized as the most important factor that impacts a product yield ramp and yield analysis of IC devices fabricated using technology nodes having minimum feature sizes of 16 nm and below.
Rapid identification and correction of manufacturing defects is important to the commercial success of an IC device. Manufacturing defects are unfortunately an inherent part of developing and producing any new IC device. Feature sizes on IC designs have continued to decrease and the complexity of fabrication process technology has continued to increase according to Moore's Law, which in-turn makes acceptable IC manufacturing yields (i.e., the number of properly functioning IC devices on each fabricated wafer) harder to achieve due to manufacturing defects. Therefore, predicting and/or characterizing the sometimes subtle effects of different types of defects on complex IC performance have become ever more important. Several testing processes have been developed for identifying and localizing specific manufacturing defects (faults) that occur within an IC device, and diagnosis of these specific faults facilitates corrective actions (e.g., changes to layout features or modifications to the fabrication process parameters) that facilitate improved production yields in subsequent fabrication runs. The sooner all design and manufacturing defects are identified and corrected, the sooner production yields for a new IC device can be improved to commercially viable levels.
Cell-aware test (defect characterization) methodologies were recently developed to address failures of conventional test and diagnosis processes to identify manufacturing defects associated with standard cells. Conventional testing processes use automatic test—pattern-generation (ATPG) tools to apply test patterns based on logic-based fault models to identify manufacturing defects. The test patterns generated in accordance with logic-based fault models typically include input pattern sets capable of detecting, for example, stuck-at and transition faults in the lowest-level IC design components and their connections. A problem with utilizing these conventional testing processes to generate test models for standard cells is that standard cells were recognized by conventional testing methods as lowest-level design components, and thus testing a given cell (e.g., a multiplexer cell or multibit cell) using test models generated from logic-based fault models often failed to recognize actual faults occurring within the cells of physical IC devices, resulting in prolonged yield ramps. Accordingly, cell-aware test methodologies were developed to generate cell-aware test models that are based on each cell's behavior in response to an exhaustive series of simulated defects that can occur at any point within the cell's layout. Cell-aware test models generated by these methodologies, when utilized by a suitable test and diagnostic system (e.g., an ATPG tool), have greatly improved test quality and accuracy of manufacturing test generation, defect diagnosis and yield analysis, whereby improving production yields more quickly that was possible using conventional testing methods. However, the effort to extract cell-aware defect behavior is not trivial—it often requires intensive effort of SPICE simulation and defect behavior classification.
Based on interactions between the present inventors and specialists in the test and diagnosis community, a current problem associated with conventional cell-aware test methodologies is that they require an extraordinary amount of time to prepare cell-aware fault models for larger standard cells such as multibit cells (i.e., cells including two or more flip-flops that respectively store data bit values). Specifically, conventional cell-aware test methods exhaustively enumerate all possible input pin value vectors/combinations (for an n-input cell, the number of combinations is 2n; i.e., two to the power of n vectors) to check whether a cell aware defect can be detected or not. This long cell-aware test processing time is a particular problem with multi-bit cells, which are usually among the largest cells in a standard library set, and which are widely used to reduce power consumption in large IC designs (e.g., more than 80% of the sequential elements implemented in some IC designs comprise multibit cells). Because each multibit cell contains multiple flip-flops, its SPICE-based netlist view is typically much larger than comparable regular design cells, so the number of defects to characterize increases accordingly. Further, the number of input pins used by a multibit cell is typically larger than regular cells, which requires a larger number of test vectors to analyze during defect characterization. As a result, cell-aware defect characterization for multibit cells using conventional methodologies takes a very long time (i.e., at least a few days, and up to weeks depending on the number of bits and the drive strength of the cell). Moreover, conventional cell-aware defect characterization methods treat each multibit cell as a single big standard cell. Accordingly, during physical-aware fault diagnosis, the fault diagnosis tool can only point to the bounding box of the big multibit cell, not to the specific location of the actual defect. For example, for scan chain failure diagnosis, the diagnosis tool usually points to the scan cell that has the defect—if such a scan cell is part of a multibit cell, the location of the defect is generally identified by the physical diagnosis tool using the bounding box of the full multibit cell, which is usually a big area in the layout.
What is needed is an improved cell-aware defect characterization methodology that substantially reduces the amount of time required to generate cell-aware test models for multibit cells in comparison to conventional methods. What is also needed is a cell-aware defect characterization methodology that provides a more detailed and accurate location of defects in multibit cells in comparison to conventional methods.